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power management may 17, 2007 1 SC416 dual synchronous buck controller with tracking start-up/shutdown features vin range 3-25v outputs adjustable from 0.75 to 5.25v, or preset output voltages: vout1 = 1.8 or 1.5v vout2 = 1.25 or 1.05v proportional or coincident tracked start-up and shut- down of both outputs adjustable soft-start rates for each output regulated shutdown for each output low shutdown power constant on-time for fast dynamic response adjustable switching frequency separated frequencies for minimal switching interac- tion: vout1 = up to 600khz vout2 = up to 720khz power save or continuous operation at light load over-voltage and under-voltage fault protection cycle-by-cycle valley current limit dc current sense using low-side rdson sensing, or rsense in source of low-side mosfet for greater accuracy separate power good outputs separate enable/power save inputs 3.1a non-overlapping gate drive smartdrive tm for high-side mosfet mlp 4x4 24 pin lead-free package industrial temperature range weee and rohs compliant applications notebook and sub-notebook graphics voltage controllers tablet pcs embedded applications ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the SC416 is a versatile, constant on-time, pseudo- xed-frequency, dual synchronous buck pwm control- ler intended for notebook computers and other battery operated portable devices. the SC416 contains all the features needed to provide cost-e ective control of two independent switchmode power supplies. the SC416 provides adjustable voltage tracking during start-up and shut-down, making it an e ective solution for a variety of applications where the voltage di eren- tial between supply rails must meet de ned limits dur- ing all operating conditions including start-up and shut- down. the SC416 supports proportional tracking which gives equal start-up and shut-down times for both out- puts, and can also provide coincident tracking where the two output voltages are equal during the lower voltages start-up and shut-down ramp. the two dc outputs are adjustable from 0.75v to 5.25v. additional features for each output include cycle-by- cycle current limit, voltage soft-start, under-voltage and over-voltage protection, programmable over-current protection, regulated shutdown, selectable power save and non-overlapping gate drive. the SC416 provides two enable/power save inputs, two soft-start inputs, two power good outputs and an on-time adjust input. the constant on-time topology provides fast dynamic response. the excellent transient response means that SC416 based solutions require less output capacitance than competing xed frequency converters. switching frequency is constant until a step in load or line voltage occurs, at which time the pulse density and frequency moves to counter the change in output voltage. after the transient event, the controller frequency returns to steady state operation. at light loads with power save enabled, the SC416 reduces switching frequency for im- proved e ciency. ? 2007 semtech corporation
SC416 2 1uf 330pf rlim2 1uf vout1 10nf vin +5v 10nf 1uf + cout1 d4 vout2 en2 q2 en1 +5v 1uf d3 +5v lx1 1 bst1 2 vdd1 3 dl1 4 en1 5 ss1 6 vout1 7 fb1 8 rtn 9 ton 10 fb2 11 vout2 12 ss2 13 en2 14 dl2 15 vdd2 16 25 pad dh2 19 ilim2 20 lx2 18 bst2 17 pgd1 22 pgd2 21 ilim1 23 dh1 24 u1 SC416 10k 10k d2 l1 pgd2 vin rton pgd1 1uf +5v vin q1 + cout2 q4 cin1 l2 cin2 q3 vout2 r1 1uf r2 d1 rlim1 vout1 r4 r3 typical application circuit
SC416 3 pin con guration marking information ordering information device package SC416mltrt (1)(2) mlpq-24 4x4 SC416evb evaluation board notes: (1) available in tape and reel only. a reel contains 3,000 devices. (2) available in lead-free package only. device is weee and rohs compliant. lx1 bst1 vdd1 dl1 en1 ss1 lx2 bst2 vdd2 dl2 en2 ss2 dh1 ilim1 pgd1 pgd2 ilim2 dh2 vout1 fb1 rtn ton fb2 vout2 gnd (pad) mlpq24: 4x4 24 lead top view 1 7 6 12 13 18 19 24 SC416 nnnn = part number (example: SC416 yyww = date code (example: 0652) xxxxx = semtech lot no. (example: 09010 xxxxx 01-10) SC416 yyww xxxxx xxxxx
SC416 4 exceeding the above speci cations may result in permanent damage to the device or device malfunction. operation outside of the parameters speci ed in the electrical characteristics section is not recommended. notes- (1) calculated from package in still air, mounted to 3 x 4.5, 4 layer fr4 pcb with thermal vias under the exposed pad per jes d51 standards. (2) tested according to jedec standard jesd22-a114-b. electrical characteristics absolute maximum ratings dhx, bstx to gnd (dc) ... -0.3 to +30v dhx, bstx to gnd (transient - 100nsec max) -2.0 to +33v lxx, ton to gnd (dc) -0.3 to +25v lxx, ton to gnd (transient - 100nsec max) -2.0 to +28v bst1 to lx1, bst2 to lx2 (dc) -0.3 to +6.0v bst1 to lx1, bst2 to lx2 (transient - 100nsec max) ..-0.3 to +7.5v dlx to gnd (dc) -0.3 to +6.0v gnd to rtn -0.3 to +0.3v vddx to rtn -0.3 to +6.0v enx, fbx, ilimx, pgdx, ssx, voutx to rtn -0.3 to vddx +0.3v peak ir re ow temperature(10-40s). 260c esd protection level (2) 2kv thermal information junction to ambient (1) 29c/w storage temperature range -60 to +150c operating junction temperature range -40 to +125c lead temperature (soldering) 10 sec . 260c parameter conditions 25c -40 to 85c units min typ max min max input supplies vin input voltage 3.0 25 v vddx input voltage 4.5 5.5 v vdd1 + vdd2 shutdown current en1, en2 = 0v 7 10 a vdd1 + vdd2 operating current en1, en2 = 5v (powersave mode) fb1, fb2 > ref 800 1200 a regulation fb1, fb2 on-time threshold 0 to 85 c -40 to 85 c 0.75 0.7425 0.7388 0.7575 0.7612 v voutx output voltage range external resistors 0.75 5.25 v vout1 on-time threshold fb1 = 5v; 0 to 85 c fb1 = 5v; -40 to 85 c 1.8 1.7775 1.7685 1.8225 1.8315 v fb1 = rtn; 0 to 85 c fb1 = rtn; -40 to 85 c 1.5 1.5 1.4812 1.4737 1.5188 1.5263 v test conditions: v in = 15v, v out = 1.5v, t a = 25 o c, 0.1% resistor dividers; rton = 1meg; vdd1/2 = 5.0v; gnd connects to pad pin.
SC416 5 parameter conditions 25c -40 to 85c units min typ max min max regulation (continued) vout2 on-time threshold fb2 = 5v; 0 to 85 c fb2 = 5v; -40 to 85 c 1.25 1.25 1.2343 1.2281 1.2656 1.2718 v fb2 = rtn; 0 to 85 c fb2 = rtn; -40 to 85 c 1.05 1.05 1.0368 1.0316 1.0631 1.0684 v voutx line regulation error 0.04 %/v voutx load regulation error 0.3 % timing voutx on-time (1) voutx set to 1.5v vout1; rton = 1meg vout2; rton = 1meg vout1; rton = 499k vout2; rton = 499k 400 330 200 167 320 260 480 400 nsec minimum on-time dh1, dh2 50 ns minimum o -time dl1, dl2 330 ns soft-start/shutdown soft-start ssx current source 5 3.5 6.5 a shutdown ssx current sink 5 3.5 6.5 a soft-start ramp time cssx = 4.7nf 700 sec ssx shutdown discharge resistance enx = rtn, voutx < 300mv 16 voutx shutdown discharge resistance enx = rtn, voutx < 300mv 16 analog inputs/outputs vout1 input resistance en1 = vdd1 120 k vout2 input resistance en2 = vdd2 90 k fbx input bias current -1 +1 a current sense ilimx source current 10 9 11 a ilimx comparator o set ilimx - gnd -10 +10 mv current limit (negative) lxx - gnd 80 60 100 mv zero crossing detector threshold lxx - gnd -7 +7 mv power good pgdx threshold 1% hysteresis typical, with respect to regulation point -12 -9 -15 % pgdx threshold delay time (2) 5s electrical characteristics (continued)
SC416 6 electrical characteristics (continued) parameter conditions 25c -40 to 85c units min typ max min max pgdx leakage 1a fault protection vdd1 under-voltage lockout vdd1 falling edge 4.0 3.7 4.35 v voutx under-voltage fault voutx falling edge -30 -35 -25 % voutx under-voltage fault delay (2) 8 clks voutx over-voltage fault +20 +17 +23 % voutx over-voltage fault delay (2) 5s thermal shutdown (2) latching, >10c hysteresis 160 c inputs/outputs en1, en2 input low voltage voutx disabled 1.2 v enx input - forced continuous mode operation enx = open ( oat) 2.0 v enx input high voltage voutx enabled, power save enabled 3.1 v enx input resistance r pull up to vddx 1.5 m r pull down to rtn 1 m fbx input low voltage 0.3 v fbx input high voltage vddx -0.3 v power good output low voltage r pgdx = 10k to vddx 0.4 v gate drivers shoot-thru protection delay (2) dhx or dlx rising 30 ns dlx pull-down resistance dl low 0.8 1.6 dlx sink current (2) v dlx = 2.5v 3.1 a dlx pull-up resistance dlx high 2 4 dlx source current (2) v dlx = 2.5v 1.3 a dhx pull-down resistance dhx low, bstx - lxx = 5v 24 dhx pull-up resistance (3) dhx high, bstx - lxx = 5v 24 dhx sink/source current (2) v dhx = 2.5v 1.3 a notes: 1) rton = 1meg. 2) guaranteed by design. 3) semtechs smartdriver? fet drive rst pulls dh high with a pull-up resistance of 10 (typical) until lx = 1.5v (typical). at this point, an additional pull-up device is activated, reducing the resistance to 2 (typical). this negates the need for an external gate or boost resistor.
SC416 7 pin descriptions pin # pin name pin function 1 lx1 switching (phase) node for vout1 2 bst1 boost capacitor connection for vout1 high-side gate drive 3 vdd1 5v power input for vout1 analog circuits and gate drive outputs. under-voltage lockout for the 5v supply is sensed on vdd1 only. 4 dl1 gate drive output for the vout1 low-side external mosfet 5 en1 enable input for vout1: ground to disable the vout1 switcher, leave open to enable vout1 switcher with power save disabled, connect to vdd1 to enable vout1 in power save mode 6 ss1 soft-start and ramped shutdown input for vout1. for independent startup connect a capacitor to rtn. for tracked startup, connect to a capacitor or to a resistor divider connected to the other output; see the voltage tracking section. 7 vout1 connect to the output capacitor of vout1 - used for on-time generation and for vout1 regulation when fb1 is connected to vdd1 or rtn 8 fb1 feedback input for vout1 - connect to an external resistor divider to adjust vout1, or connect to rtn or vdd1 to select internal feedback. 9 rtn analog return (ground) for both vout1 and vout2 10 ton on-time adjust input - connect a resistor from vin to ton to program the on-time - the on-time one-shot for vout1 is internally set at 20% greater than for vout2 to prevent frequency interaction between the two con- verters 11 fb2 feedback input for vout2 - connect to an external resistor divider to adjust vout2 or connect to rtn or vdd2 to select internal feedback 12 vout2 connect to the output capacitor of vout2 - used for on-time generation and for vout2 regulation when fb2 is connected to vdd2 or rtn 13 ss2 soft-start and ramped shutdown input for vout2. for independent startup connect a capacitor to rtn. for tracked startup, connect to a capacitor or to a resistor divider connected to the other output; see the voltage tracking section. 14 en2 enable input for vout2 - ground to disable the vout2 switcher - leave open to enable vout2 switcher with power save disabled - connect to vdd2 to enable vout2 in power save mode 15 dl2 gate drive output for the vout2 low-side external mosfet 16 vdd2 5v power input for vout2 analog circuits and gate drive outputs. vdd2 must connect to the same supply as vdd1. 17 bst2 boost capacitor connection for vout2 high-side gate drive 18 lx2 switching (phase) node for vout2 19 dh2 gate drive output for the vout2 high-side external mosfet 20 ilim2 current limit input for vout2 - connect through a resistor to the drain of the vout2 low-side mosfet 21 pgd2 open-drain power good output for vout2 22 pgd1 open-drain power good output for vout1 23 ilim1 current limit input for vout1 - connect through a resistor to the drain of the vout1 low-side mosfet 24 dh1 gate drive output for the vout1 high-side external mosfet t pad power ground for vout1 and vout2 gate drivers and thermal pad for heatsinking
SC416 8 block diagram SC416 block diagram en1 drv dh1 drv vdd1 lx1 bst1 s q r qb dl1 uv- ov monitor ton ilim1 ton1 one-shot reference fb1 pgd1 vout1 vdd2 ref vdd1 drv dh2 drv vdd2 lx2 bst2 s q r qb dl2 monitor ilim2 ton2 one-shot fb2 pgd2 vout2 ton ton1 ss1 gnd fb2 select fb1 select ref vdd1 en2 ss2 vdd2 vdd1 lx1 valley ilim/ zcd detect lx2 valley ilim/ zcd detect pad rtn ss1 control ss2 control ref uv- ov vin vin ton2 fb1 comparator fb2 comparator
SC416 9 applications information SC416 synchronous buck controller the SC416 is a dual synchronous controller which sim- pli es the task of designing a dual-output power sup- ply with synchronized or tracking ramps for startup and shutdown. vin and +5v bias supplies the SC416 requires an external +5v bias supply in ad- dition to the vin supply. if stand-alone capability is re- quired, the +5v supply can be generated with an exter- nal linear regulator. pseudo-fixed frequency constant on-time pwm controller the pwm control method for each output is a constant- on-time, pseudo- xed frequency pwm controller, see figure 1. the ripple voltage seen across the output ca- pacitors esr provides the pwm ramp signal. the on-time is determined by an internal one-shot whose period is proportional to output voltage and inversely proportion- al to input voltage. a separate one-shot sets the mini- mum o -time (typically 330ns). the two converters are designed to operate at di erent frequencies to reduce interaction; side2 frequency is set typically 20% higher than side1. q1 q2 l c out vin esr + c in v out fb threshold 750mv v fb v lx v lx ton fb r1 r2 figure 1 on-time one-shot (ton) each internal on-time one-shot comparator has two in- puts. one input looks at the output voltage via the vout pin, while the other input samples the input voltage via the ton pin and converts it to a proportional cur- rent. this current charges an internal on-time capacitor. the ton on-time is the time required for this capacitor to charge from zero volts to vout, thereby making the on-time directly proportional to output voltage and in- versely proportional to input voltage. this implementa- tion results in a fairly constant switching frequency with no clock generator. the nominal frequency is set through an external resis- tor rton connected between vin and the ton pin. to minimize interaction between the two converters, side2 is set to operate at a slightly higher frequency. the gen- eral equations for the side1 and side2 on-times are: ton1 = 3.30 (rton + 37) (vout/vin) + 35 ton2 = 2.75 (rton + 37) (vout/vin) + 35 (ton in nsec, rton in k) switch-mode operation the switch-mode operation is explained below, and is identical for both sides except for the ton timing. the output voltage is sensed at the fb pin and is com- pared to the internal 750mv reference. (the output volt- age can also be sensed at the vout pin which uses an internal resistor divider, see vout voltage selection.) when the sensed voltage drops below 750mv, this trig- gers a single ton pulse, which is fed to the dh high-side driver. the dh pulse-width follows ton according to the ton equation, and after that time dh drives low to shut o the high-side mosfet. after dh drives low, the dl output drives high to energize the low-side mosfet. once high, dl has a minimum pulse width of typically 330nsec which is the minimum o -time. at the end of the minimum o -time, dl continues to stay high until
SC416 10 one of the following occurs: the fb comparator input drops to the 750mv reference, as sensed through the fb pin or the vout pin the zero cross detector trips, if psave is active the negative current limit detector trips if dl drives low because fb has dropped to 750mv, then another dh on-time is started. this is normal operation at heavy load (fully synchronous operation with either dh or dl high except during transitions). the zero cross detector monitors the voltage across the low-side mosfet during the dl high time and detects when it reaches zero. if dl drives low because of the zero cross detector, and psave is active, then both dh and dl will remain low until fb drops to 750mv, at which point the next dh on-time will begin. if a zero cross is detected on eight consecutive cycles, then for each sub- sequent switching cycle dl will shut o when the zero cross detector trips; see the psave operation section. when this occurs, both dh and dl will stay low until fb drops to 750mv, which will begin the next dh on-time. this is normal operation at light load, see the psave op- eration section. the negative current limit detector trips when the drain voltage at the low-side mosfet reaches +80mv, indicat- ing that a large negative current ows through the induc- tor from vout. when this occurs, dl drives low. both dh and dl will then stay low until fb drops to 750mv, which will begin the next dh on-time. tripping negative cur- rent limit is rare. to help reduce noise interaction between sides, the ris- ing edge of each dh driver is inhibited momentarily if the other side is switching. for example, if side1 is perform- ing a dh or dl transition (up or down), then side2s dh driver is held o for roughly 30nsec to allow side1 to nish switching. ? ? ? applications information (continued) vout voltage selection output voltage is regulated by comparing vout as seen through a resistor divider to the internal 750mv refer- ence, see figure 2. each output can be adjusted to a volt- age between 0.75 C 5.25v. the output voltage is set by the equation: v out = 0.75 ? (1 + r1/r2) r1 r2 vout to fb pin figure 2 note: the parallel resistance of r1 and r2 should not be less than 2k. using a smaller resistance can cause the ic to default to the internal preset output voltages shown below. there are xed output voltages accessible through each fb pin. if the fb pin is connected to either rtn or +5v, then the ic will ignore the fb pin and instead regulate the output voltage using the vout pin which is connect- ed to internal resistors. the voltage selections available are as shown: fb internal voltage selection fbx = rtn fbx = +5v side1 1.5v 1.8v side2 1.05v 1.25v note that each fb input operates independently.
SC416 11 applications information (continued) enable/psave inputs each converter has a separate enable pin. each en input operates as follows: en = gnd. this turns the converter o . en = open ( oat). this turns the converter on with psave mode disabled (continuous conduction mode). in this case, the en pin will oat to approximately 2v due to an internal 1.5meg/1meg resistor divider from +5v to ground. en = high (3.1v min). this turns the converter on with psave mode enabled. at light loads, the converter will operate in psave mode. note that the two en pins are separate, so each output can be disabled or operated with or without psave inde- pendently. for tracking operation during startup, the two en pins are typically tied together; see the voltage tracking sec- tion. if both en1 and en2 are grounded, the device is placed into the lowest-power state, drawing typically 7a from the +5v supply. psave operation each output provides automatic psave operation at light loads if the enx pin is set high. the internal zero-cross comparator looks for inductor current (via the voltage across the lower mosfet) to fall to zero on eight con- secutive switching cycles. once observed, the control- ler enters psave mode and turns o the low-side mos- fet on each subsequent cycle when the current crosses zero. to add hysteresis, the on-time is also increased by 25% in psave, for that converter only; it does not a ect the other converters on-time. the e ciency improve- ment at light loads more than o sets the disadvantage of slightly higher output ripple. if the inductor current does not cross zero on any switching cycle, the controller immediately exits psave. once psave is exited, it requires 8 switching cycles at light load to re-enter psave. since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. this allows the output voltage to recover quickly in response to negative load steps. when operating in psave mode at light loads, the lx waveform will not have the typical square wave shape seen when operating in continuous conduction mode. shortly after dl drives low, and both mosfets are o , the lx voltage will show ringing. this ringing is caused by the lc circuit formed by the inductor and device ca- pacitance of the mosfets and low-side diode. when the low-side mosfet turns o the inductor current falls toward zero. when it reaches zero, the inductance and mosfet capacitances will tend to ring freely. this is nor- mal psave operation as shown in figure 3. vout vin cout l c q1 c q2 q1 q2 dh dl dl lx vout vin typical ringing at lx figure 3
SC416 12 applications information (continued) smart psave protection in some applications, circuits connected to vout can leak current from a higher voltage and thereby cause vout to slowly rise and reach the ovp threshold, causing a hard shutdown; the SC416 uses smart psave to prevent this. when the output voltage exceeds 8% above nominal (810mv at fb), that converter then exits psave (if already active), and dl drives high to energize the low-side mos- fet. this will draw current from vout via the inductor causing vout to fall. when fb drops to the 750mv trip point, a normal ton switching cycle begins. this meth- od cycles energy from vout back to vin and prevents a hard ovp shutdown, and also minimizes operating power by avoiding continuous conduction-mode opera- tion. if a light load is present, dh/dl switching continues for 8 consecutive cycles and then the ic returns to psave mode to reduce operating power. current limit for current limiting, the rdson of the lower mosfet can be used as a current sensing element, or a sense resistor at the lower mosfet source can be used if greater accu- racy is needed. rdson sensing is more e cient and less expensive. in both cases, the rilim resistor sets the over- current threshold. rilim connects from the ilim pin to ei- ther the lower mosfet drain (for rdson sensing) or the high side of the current-sense resistor. rilim connects to a 10a current source from the ilim pin which turns on when the low-side mosfet is on (dl is high). if the voltage drop across the sense resistor or low-side mos- fet exceeds the voltage across rilim, then the voltage at the ilim pin will be negative or below gnd, and current limit will activate. the high-side mosfet is not allowed to turn on until the voltage drop across the sense resis- tor or mosfet falls below the voltage across the rilim resistor (ilim pin reaches gnd). if the overload at the output continues, the dh pulses will get farther apart, and the output voltage will fall. eventually the output will fall enough to cause fb to drop to 525mv, activat- ing the under-voltage protection and shutting down the converter. the current sensing scheme actually regulates the induc- tor valley current, (see figure 4). this means that if the current limit is set to 10a, the peak current through the inductor would be 10a plus the peak ripple current, and the average current through the inductor would be 10a plus ? the peak-to-peak ripple current. i limit i load i peak inductor current time valley current limit figure 4 the rdson sensing circuit is shown in figure 5 with ril- im = r1 and rdson of q2. d1 vout +5v vin + cin q2 + c3 d2 r1 pad dl vdd ilim lx dh bst c2 q1 l figure 5 the resistor sensing circuit with rilim = r1 and rsense = r4 is shown in figure 6.
SC416 13 applications information (continued) q1 q2 + cin vout l1 + c3 d2 pad dl vddp ilim lx dh bst vin c2 r4 r1 d1 +5v figure 6 the following over-current equation can be used for both rdson or resistive sensing. for rdson sensing, the mosfet rdson rating is used for the value of rsense. iloc(valley) = 10a rilim / rsense power good output each output provides a power good (pgd) output, which is an open-drain output requiring a pull-up resistor. when the output voltage as sensed at fb is -9% from the 750mv reference (682mv), pgd is pulled low. it is held low until the output voltage returns above -9% of nomi- nal; the falling edge of vout does not latch pgd. pgd is held low during start-up and will not be allowed to tran- sition high until soft-start is completed, when ss reaches 750mv. there is a 5sec delay built into the pgd circuit to prevent false transitions. pgd also transitions low if the fb pin exceeds +20% of nominal (900mv), which is also the over-voltage shut- down point. output over-voltage protection (ovp) when fb exceeds 20% of nominal (900mv), dl latches high and the low-side mosfet is turned on. dl stays high and the output stays o until the en/psv input is toggled or vdd is recycled. there is a 5s delay built into the ovp detector to prevent false transitions. pgd is also held low after an ovp. output under-voltage protection (uvp) when fb falls 30% below nominal (to 525mv) for eight consecutive clock cycles, the output is shut o ; the dl/ dh drives are pulled low to tri-state the mosfets, and the converter stays o until its en/psv input is toggled or the +5v supply at vdd1 supply is recycled. the other output remains on during a uvp event. por and uvlo under-voltage lockout circuitry (uvlo) inhibits switch- ing and tri-states all dh/dl drivers until the +5v supply at vdd1 rises above 4.4v. an internal power-on reset (por) occurs when vdd1 exceeds 4.4v, which resets the fault latches and quickly discharges the soft-start capacitors to prepare the pwm for startup switching. at this time the SC416 will exit uvlo and begin the startup cycle. startup sequence the startup sequence for each output relies on an exter- nal ramp at the ss pin. during startup, the fb comparator uses the ss ramp voltage as the reference until ss reach- es 750mv, at which point the fb comparator switches over to the internal 750mv reference. the external ramp is typically created by connecting a capacitor to the ss pin, which will be charged by a constant current. or, the ss pin can be connected to an external ramp provided by the other outputs ramp-up as seen through a resistor divider. see the voltage tracking section. before starting, with en low, the ss pin is internally tied to gnd through 4k. when en is released, ss is brie y pulled to gnd through 16 ohms to discharge the ss ca- pacitance. then the resistances are removed, startup be- gins, and a 5a source current ows out of the ss pin.
SC416 14 if an external capacitor is connected to ss, with no other components, then the 5ua current into the capacitor cre- ates a linear voltage ramp. the internal fb comparator tracks this ss ramp, which forces vout to track the ss ramp. the time in msec needed for the ss ramp to reach the 750mv reference is: t start = css 150 (t start in sec, css in nf) at the end of this time, the ss pin has reached 750mv and the output voltage is at its nominal value. the fb comparator then switches over to the internal 750mv ref, and the ss pin is thereafter ignored. the 5a cur- rent source remains on, so the css capacitor continues to charge up to +5v. the ss pin can be connected to a capacitor to provide a programmable ramp, or connected to a resistor divider from the other output to provide a synchronized startup, see the voltage tracking section. the startup waveforms when using a capacitor for the voltage ramp are shown in figure 7. en vout 5v ss 750mv ss linear ramp: 5ua current source into css css ss en SC416 t start figure 7 applications information (continued) shutdown sequence each output has a controlled shutdown. the ramp-down sequence is optimized for use with an external ss capaci- tor. when the en pin is set low, psave mode is disabled and the shutdown sequence begins. the ss pin stops sourcing 5ua, and an internal 4k pulldown resistor is en- abled along with a 5ua current sink. the 4k resistor helps discharge of the ss capacitor (if used), which was previ- ously charged to +5v by the 5ua current source. the ss capacitor discharges quickly; when the ss voltage reach- es 810mv, the 4k resistor is released, leaving the 5a cur- rent sink on (current into the ss pin), which discharges the ss capacitor from 810mv to 750mv at a slower rate. when the ss voltage reaches 750mv, the ramp-down at vout begins. with ss at 750mv, the fb comparator ig- nores the internal 750mv reference and instead uses the ss ramp-down to regulate vout. as the ss pin ramps down from 750mv due to the current sink, vout follows the ss pin in a linear ramp-down. note that psave is disabled during the shutdown cycle to allow vout to actively track the ss ramp-down, even with no load. the ramp-down continues until vout falls to 300mv as sensed at the vout pin, not the fb pin. at this point the switching is disabled, the dh and dl drivers are set low (both mosfets o ), and an internal 16 ohm pulldown connects to the vout pin to nish soft-discharge of the output.
SC416 15 the general shutdown waveforms are shown in figure 8. 300mv: switching stops en vout linear down-ramp soft-discharge into 16 ohms linear down-ramp +5v 750mv: vout down-ramp begins 810mv: ss linear down-ramp begins rapid css discharge into 4kohm vout ss t sd_delay t sd_ramp css ss en SC416 figure 8 note that due to the discharging of css from +5v to 750mv, there is a small delay between en going low and vout beginning to ramp down. the delay is given by the equation: t sd_delay = css 19 (t sd_delay in sec, css in nf) after this delay, the time for the output to ramp down to the switch-o point of 300mv is given by: t sd_ramp = css 150 ? (1 C 300mv/vout) (t sd_ ramp in sec, css in nf) once the output reaches 300mv, the shutdown sequence is complete. dh and dh stop switching, the internal 16 ohm discharge pulldown at vout is energized, and that side will go to the lowest-power state. voltage tracking the SC416 provides voltage tracking during both start- up and shutdown. the use of the ss pins determines the type of tracking. the two most common tracking schemes are proportional and coincident tracking. proportional tracking (fb tracking) proportional tracking causes the output waveforms to have the same startup and shutdown ramp time as shown in figure 9. vout1 t start 300mv en1 en2 ss1 ss2 750mv rapid discharge of ss capacitor +5v vout2 en1 en2 ss1 ss2 SC416 css t sd_ramp figure 9 for proportional tracking, the two ss pins are tied togeth- er to share the same voltage ramp. the two en pins must also be tied together. since the ss pins are tied together, the startup and shutdown ramps for each side will track the same signal. note that during startup and shutdown, the fb pins for each side will track the same ss signal; this method can also be called fb tracking. startup for proportional tracking (fb tracking) is as fol- lows. when both en pins are set high simultaneously, each ss pin sources 5ua. by connecting the ss pins to- gether, the startup ramp rates for both fb1 and fb2 are forced to be the same. since the total current source is applications information (continued)
SC416 16 10a instead of 5a, the css capacitor must be twice as large as in the independent case. it is acceptable to use only one ss capacitor for both ss pins, and the startup time follows the equation: t start = css 75 (t start in sec, css in nf) once the ss pins reach 750mv, each fb comparator switches over to the internal 750mv reference, and the ss pin is ignored. css will continue to charge to +5v, just as in the independent case. shutdown for proportional tracking is similar to the inde- pendent case. both en pins are simultaneously pulled to gnd to start the shutdown sequence. when the en pins are set low, the two ss 5a current sources are disabled, and the internal 4k pull-down of each ss pin is energized. this begins a quick discharge of css from the initial +5v starting point. when css discharges down to 810mv, each 4k resistor is removed and each ss 5a current sink is energized, to cause a more gradual ramp down to 750mv. when ss reaches 750mv, each fb comparator ignores the inter- nal 750mv reference and uses the falling ss ramp as the reference. this causes both fb pins to fall at a constant linear rate. this in turn causes both vouts to fall linearly. this continues for each vout until it reaches 300mv, at which point all switching for that output will stop. note that the output ramp-down is controlled only until the point where the output voltage (as sensed at the vout pin, not the fb pin) reaches 300mv, and then switching stops. also note that the two output voltages may not reach 300mv at the same time. with propor- tional tracking, the lower voltage will reach 300mv rst; at that point, the lower voltage will enter soft-discharge into 16 ohms, but the other output will continue on the ss ramp-down until it also reaches 300mv. for the ma- jority of applications this is acceptable since 300mv is typically too small to cause a voltage-di erential prob- lem for the load. applications information (continued) coincident tracking (vout tracking) coincident tracking has the lower output actively match- ing the higher output during startup and shutdown. during startup, the two voltages track identically until the lower vout reaches its nominal point and then re- mains at that point. the higher voltage continues on a linear ramp until reaching its nal value. during shutdown, the higher voltage initially starts to fall while the lower voltage stays in regulation. when the higher voltage has dropped to the same level as the low- er voltage, the lower voltage joins the ramp-down, and both voltages fall at the same rate. when the outputs reach 300mv, switching stops and the outputs will soft- discharge into their vout pins. the waveforms and schematic for coincident tracking are shown in figure 10. vout1 t start 300mv en1 en2 ss1 750mv rapid discharge of ss capacitor +5v vout2 en1 en2 ss1 SC416 css t sd_ramp ss2 vout1 vout2 r3 r4 r1 r2 fb2 figure 10 note that both en pins are tied together. for coincident tracking, the higher output voltage must act as the con- trol, and the lower output must be the follower. either side can act as controller or follower. in this case, vout1 is the higher output voltage. when the en pins are set
SC416 17 high, both outputs start switching. ss1 is connected to a capacitor and therefore vout1 will follow the normal (independent) startup and shutdown operation. ss2 does not have the typical capacitor connection; in- stead ss2 connects to vout1 through resistor divider r3/r4, which forces the ss2 voltage to be proportional to vout1. as vout1 rises during startup, ss2 also rises, and the fb2 comparator will force vout2 to track ss2 until ss2 reaches 750mv. note that fb2 sets the output voltage for vout2 through r1/r2. by setting the same ratio for r3/r4 as r1/r2, vout2 is forced to track vout1. this tracking continues until fb2 reaches 750mv, at which point vout2 ignores the ss2 ramp and switches over to the internal 750mv reference. ss2 will continue to rise above 750mv since it is connected to vout2 which continues to rise to its nominal value. note that during this time the ss2 pin will source 5ua, as if it were charging a capacitor. this current will ow through into r3/r4 and create an o set voltage at ss2. the full equation for ss2 voltage is: vss2 = vout1 (r4 / (r3 + r4) + 5a (r3||r4) the term for the ss2 o set is (5a r3||r4). when track- ing vout1 during startup, ss2 will be slightly higher than the ideal value due to this o set term. this o set at ss2 is tracked by fb2. because of the fb2 resistor divider, this causes a consequently higher o set at vout2. the net e ect is that vout2 will be slightly higher than vout1 during startup tracking. the net o set is given by the following equation, where r5/r6 are the top and bottom resistor values used for the fb2 resistor divider: vout1 C vout2 = 5a (r3||r4) (1 + r5/r6) applications information (continued) since the ratio of r5/r6 is dictated by the output voltage, the way to minimize the o set is to reduce r3 and r4. it is recommended to set the r3/r4 parallel combination to 1k max, which limits the ss2 o set to 5mv. for shutdown, both en pins are pulled low to start the shutdown sequence. the higher output falls rst (vout1 in this case) as described in the independent case. the ss2 pin also falls as vout1 falls. when ss2 has reached 750mv, the ramp-down of vout2 begins. the fb2 com- parator switches over to the ss2 pin and tracks ss2 as it ramps down. ss2s ramp-down is in turn controlled by the ramp-down of vout1. note that during the initial time when both en pins pulled low, the internal 4k pulldown on ss2 is ener- gized, along with the 5ua current sink. the connecting of the 4k pulldown a ects the ss2 voltage, causing it to be signi cantly lower than predicted by the r3/r4 divider. if the ss2 voltage suddenly shoots below 750mv, this will cause the fb2 comparator to ignore the internal 750mv reference and switch over to the ss2 voltage. also, the 4k resistor is released, which causes the ss2 voltage to go back above 750mv, since ss2 will now track vout1 through r3/r4. this can create an unwanted overshoot on vout2. this is easily prevented by placing a 10nf ca- pacitor across r4, to prevent sudden changing of the ss2 voltage. modi ed coincident tracking (vout proportional tracking) a modi cation of coincident tracking is to set r3/r4 (ss2 resistor divider) to a ratio other than r1/r2 (fb1 resistor divider). vout2 will still track ss2 during startup and shutdown, but vout2 can be made to ramp either quick- er or slower than vout1, based on the r3/r4 ratio, see figure 11.
SC416 18 applications information (continued) figure 11 note that r3/r4 must never exceed the fb resistor ra- tio for vout1. if this were the case, ss2 cannot exceed 750mv, and the fb2 comparator would never switch over to the internal 750mv reference: vout2 would not complete its startup cycle and would not reach the nomi- nal regulation point. to prevent this it is recommended to set r3/r4 such that ss2 is greater than 850mv when vout1 is at the nominal point. mosfet gate drivers the dh and dl drivers are optimized to drive moderate high-side and larger low-side power mosfets. an adap- tive dead-time circuit monitors the dl output and pre- vents the high-side mosfet from turning on until dl is fully o ; another circuit monitors the dh output and pre- vents the low-side mosfet from turning on until dh is fully o . note: be sure there is low resistance and low inductance between the dh and dl outputs to the gate of each mosfet. smartdrive tm each side uses semtechs proprietary smartdrive to re- duce switching noise. the dh drivers will turn on the high-side mosfet at a lower rate initially, allowing a soft- er, smooth turn-o of the low-side diode. once the diode is o , the smartdrive circuit automatically drives the high- side mosfet on at a rapid rate. this technique reduces switching less while maintaining high e ciency, and also avoids the need for snubbers or series resistors in the gate drive. figure 12 design procedure prior to designing a switch mode supply, the input volt- age, load current, and switching frequency must be speci ed. the maximum input voltage (vinmax) is de- termined by the highest ac adaptor voltage, and the minimum input voltage (vinmin) is determined by the lowest supply voltage after accounting for voltage drops due to connectors, fuses, and switches. in general, four parameters are needed to de ne the de- sign: nominal output voltage (vout) static or dc output tolerance transient response maximum load current (iout) 1. 2. 3. 4. vout1 t start 300mv en1 en2 ss1 750mv rapid discharge of ss capacitor +5v vout2 r3/r4 > r1/r2 r3/r4 < r1/r2 t sd_ramp en1 en2 ss1 SC416 css ss2 vout1 vout2 r3 r4 r1 r2 fb2
SC416 19 applications information (continued) there are two values of load current to consider: con- tinuous load current and peak load current. continuous load current is concerned with thermal stresses which drive the selection of input capacitors, mosfets and diodes. peak load current determines instantaneous component stresses and ltering requirements such as inductor saturation, output capacitors and design of the current limit circuit. design example: side1 will be used. vin = 10v min, 20v max vout1 = 1.8v +/- 4% load = 10a maximum inductor selection low inductor values result in smaller size but create high- er ripple current. higher inductor values will reduce the ripple current but are larger and more costly. because wire resistance varies widely for di erent inductors and because magnetic core losses vary widely with operating conditions, it is often di cult to choose which inductor will optimize e ciency. the general rule is that higher inductor values have better e ciency at light loads due to lower core losses and lower peak currents, but at high load the smaller inductors are better because of lower re- sistance. the inductor selection is generally based on the ripple current which is typically set between 20% to 50% of the maximum load current. cost, size, output ripple and e ciency all play a part in the selection process. the rst step is to select the switching frequency. in this case vout1 will be used at a nominal 270khz. for 15v input and 1.8v output, the typical on-time should be: tontyp = vout/vin/frequency tontyp = 444nsec. the timing resistor rton is selected to provide tontyp: rton = (tontyp C 35) (vin / (3.3 vout) C 37 rton = 976k. we will use rton = 1meg. note that side2 will run typically 20% faster than side1, in this case 320khz. during the dh on-time, voltage across the inductor is (vin - vout). to determine the inductance, the ripple current must be de ned. smaller ripple current will give smaller output ripple and but will lead to larger inductors. the ripple current will also set the boundary for psave opera- tion. the switcher will typically enter psave operation when the load current decreases to ? of the ripple cur- rent; (i.e. if ripple current is 4a then psave operation will typically start for loads less than 2a. if ripple current is set at 40% of maximum load current, then psave will oc- cur for loads less than 20% of maximum current). the equation for inductance is: l = (vin - vout) ton / i ripple use the maximum value for vin, and for ton use the val- ue associated with maximum vin, and that sides ton us- ing the rton value selected. for selecting the inductor, we start with the highest vout setting and a maximum ripple current of 4a. ton1 = 343 nsec at 20vin, 1.8vout l = (20v - 1.8v) 343 nsec / 4a = 1.56h we will use 1.5h which will slightly increase the maxi- mum i ripple to 4.2a. note: the inductor must be rated for the maximum dc load current plus ? of the ripple current. the minimum ripple current is also calculated. this oc- curs when vin is at the minimum value of 10v. ton vinmin = 3.3 (rton + 37) (vout/vin) + 35 ton vinmin = 651nsec i ripple = (vin - vout) ton / l i ripple_vinmin = (10 C 1.8) 651nsec / 1.5h = 3.55a
SC416 20 applications information (continued) capacitor selection the output capacitors are chosen based on required esr and capacitance. the esr requirement is driven by the output ripple requirement and the dc tolerance. the output voltage has a dc value that is equal to the valley of the output ripple, plus ? of the peak-to-peak ripple. changing the ripple voltage will lead to a change in dc output voltage. the design goal is +/-4% output regulation. the internal 750mv reference tolerance is 1%, and assuming 1% toler- ance for the fb resistor divider, this allows 2% tolerance due to vout ripple. since this 2% error comes from ? of the ripple voltage, the allowable ripple is 4%, or 72mv for a 1.8v output. although this is acceptable from a regula- tion standpoint, 72mv ripple is high for a 1.8v output and therefore more realistic ripple value of 36mv will be used (2% of vout). the maximum ripple current of 4.2a creates a ripple volt- age across the esr. the maximum esr value allowed would create 36mv ripple: esr max = v ripple /i ripplemax = 36mv / 4.2a esr max = 8.6 m while the esr is chosen to meet ripple requirements, the output capacitance (f) is typically chosen based on transient requirements. a worst-case load release, from maximum load to no load at the exact moment when in- ductor current is at the peak, de nes the required capaci- tance. if the load release is instantaneous (load changes from maximum to zero in a very small time), the output capacitor must absorb all the inductors stored energy. this will cause a peak voltage on the capacitor according to the equation: cout min = l (iout + 1/2 i ripplemax ) 2 ___________________ (v peak 2 - vout 2 ) with a peak voltage vpeak of 1.98v (180mv or 10% rise above 1.8v upon load release), the required capacitance is: cout min = 1.5h (10 + 1/2 4.2) 2 ___________________ (1.98 2 - 1.8 2 ) cout min = 323f the previous requirements (323f, 6.4m) will be met using a single 330f 6m device. note that output voltage ripple is often higher than ex- pected due to the esl (inductance) of the capacitor. see the fb/vout ripple section. if the load release is relatively slow, the output capaci- tance can be reduced. at heavy loads during normal switching, when the fb pin is above the 750mv refer- ence, the dl output is high and the low-side mosfet is on. during this time, the voltage across the inductor is approximately -vout. this causes a down-slope or fall- ing di/dt in the inductor. if the load di/dt is not much faster than the di/dt in the inductor, then the inductor current can track the changing load current, and there will be relatively less overshoot from a load release. the following can be used to calculate the needed capaci- tance for a given diload/dt. peak inductor current: il peak = iload max + 1/2 i ripplemax il peak = 10 + 1/2 4.2 = 12.1a rate of change of load current = diload/dt imax = maximum dc load current = 10a cout = il peak (l il peak / v out - imax/(diload /dt)) ___________________________________ 2 (v peak - vout) example: load di/dt = 2.5a/sec
SC416 21 applications information (continued) this would cause the output current to move from 10a to zero in 4sec. cout = 12.1 (1.5h 12.1 / 1.8 - 10 / (2.5a/1sec)) ____________________________________ 2 (1.98 - 1.8) cout = 204f note that 204f is less than the 323uf needed to meet the harder (instantaneous) transient load release. stability considerations unstable operation shows up in two related but distinct- ly di erent ways: fast-feedback loop instability due to in- su cient esr and double-pulsing. loop instability can cause oscillations at the output as a response to line or load transients. these oscillations can trip the over-voltage protection latch or cause the output voltage to fall below the tolerance limit. the best way for checking stability is to apply a zero-to-full load transient and observe the output voltage ripple envelope for over- shoot and ringing. over one cycle of ringing after the ini- tial step is a sign that the esr should be increased. SC416 esr requirements the on-time control used in the SC416 regulates the valley of the output ripple voltage. this ripple voltage consists of a term generated by the esr of the output capacitor and a term based on the capacitance charging and discharging during the switching cycle. a minimum esr is required to generate the required ripple voltage for regulation. for most applications the minimum esr ripple voltage is dominated by pcb layout and the prop- erties of the output capacitors, typically sp or poscap devices. for stability the esr zero of the output capacitor should be lower than one-third the switching frequency. the formula for minimum esr is: esrmin = 3 / (2 cout freq) for applications using ceramic output capacitors, the esr is generally too small to meet the above criteria. in these cases it is possible to create a ripple voltage ramp that mimics the esr ramp. this virtual esr ramp is created by integrating the voltage across the inductor, and coupling the signal into the fb pin as shown in figure 13. r1 r2 to fb rl cl cc cout l dl dh vin figure 13 double-pulsing double-pulsing occurs because the ripple waveform seen at the fb pin is either too small, or because the fb and vout ripple waveforms are very noisy and prone to cause premature triggering of the fb comparator. both are discussed below. increasing fb ripple if the ripple waveform at fb is too small, the fb waveform will be susceptible to switching noise. note that under normal conditions the fb voltage is within 10-20mv of the 750mv trip point. noise can couple into the fb point from either side1 or side1, or from an external circuit. this causes the fb comparator to trigger too quickly after the 330ns minimum o -time has expired. double-pulsing will result in higher ripple voltage at the output but in most cases is harmless. a way to remedy this is to couple more ripple into fb from vout. note that the feedback resistor divider at- tenuates the fb ripple. this can be compensated by placing a small capacitor in parallel with the top resistor, which e ectively increases the ripple that appears at fb.
SC416 22 the schematic with added capacitor c is shown below. r1 r2 to fb c cout vout figure 14 this capacitor should be left out until con rmation that double-pulsing exists. it is best to leave a spot on the pcb in case it is needed. fb/vout ripple because the constant on-time control method triggers a dh pulse whenever the fb waveform reaches the 750mv trip point, it is important that the vout and fb ripple waveforms are well shaped. this waveform will depend on the output capacitors. the idealized case for the output lter has an inductor and a capacitor cout with series esr. the voltage ripple due to charging and discharging cout is typically much smaller than the ripple voltage due to esr, so the over- all ripple waveform is generally determined by esr only. the result is a well-de ned sawtooth, see figure 15. applications information (continued) figure15 in many applications, the output capacitor also has some series inductance (esl), and this can have a large e ect on ripple. the ripple current creates voltage across the esl; this is a square wave similar to the lx waveform. the result is shown below. note the fast rising and falling edges created by the esl. r1 r2 to fb cout vout load lx esr inductor ripple current vout ripple from esr fb ripple 750 mv
SC416 23 r1 r2 to fb cout vout load lx esr ripple current vout ripple from esr fb ripple 750 mv esl vout ripple from esl total vout ripple figure 16 note also that the e ect of esl becomes increasingly more noticeable with lower vout and higher vin. the square wave due to esl is basically the same square wave seen at the lx node, scaled down by the ratio of the output inductor and the esl. as vout gets lower, the output inductor gets smaller, and this directly increases the esl square wave. moreover, lower output voltages have tighter ripple requirements, so there is generally less room available for pk-pk ripple. in addition to the esl, most applications also have a small capacitor in parallel with cout; this is typically a small ceramic capacitor intended to absorb high frequency noise not ltered by the output capacitor, as shown by cb in figure 17. r1 r2 to fb cout vout load lx esr esl cb figure 17 this capacitor cb can have a large e ect on the ripple waveform. the switch transitions are fast, typically 10- 30nsec. at this high speed, the output capacitor (cout) impedance is dominated by esl, which is in parallel with cb. the e ective circuit is a parallel l-c lter. the choice of cb can have signi cant e ect on the ripple waveform. this parallel lc circuit can lead to ringing at vout. since the fb waveform goes below the 750mv threshold soon after the dh pulse is nished, there is the potential for double-pulsing; the ringing can cause the fb waveform to go below the trip point too early. applications information (continued)
SC416 24 figure 18 shows examples of this. fb trip point fb trip point false trigger on fb false trigger on fb idealized esl ripple actual ripple with cbp idealized esl ripple figure 18 there are two ways to deal with this issue. one is to use a larger ceramic capacitor, typically 2.2C10f, which sig- ni cantly smooths the ripple waveform as shown in fig- ure 19. large cb (~2.2 ? 10 uf) fb trip point actual ripple with cbp ripple due to esl figure 19 a second solution is to add a small rc lter in series with the fb resistors, shown by rf/cf in figure 20. this rc lter is intended to remove the high-frequency noise but still allow the ripple to reach the fb pin. recommended values are 10 ohms and 10nf. r1 r2 to fb cf vout rf vout ripple fb ripple figure 20 dropout performance the vout adjust range for continuous-conduction op- eration is limited by the xed 330nsec (typical) minimum o -time one-shot. when working with low input voltag- es, the duty-factor limit must be calculated using worst- case values for on and o times. the ic duty-factor limitation is given by: duty = ton min / (ton min + toff max ) be sure to include inductor resistance and mosfet on- state voltage drops when performing worst-case drop- out duty-factor calculations. SC416 system dc accuracy (vout controller) three factors a ect vout accuracy: the trip point of the fb error comparator, the switching frequency variation with line and load, and the external resistor tolerance. the error comparator is trimmed to trip when the fb pin is 750mv, +/-1% over the range of 0 to 85 c . applications information (continued)
SC416 25 the on-time pulse is programmed using the rton resis- tor to give a desired frequency. however, some frequen- cy variation with line and load is expected. this variation changes the output ripple voltage. because constant on- time converters regulate to the valley of the output rip- ple, ? of the output ripple appears as a dc regulation er- ror. for example, if the output ripple is 50mv with vin = 6 volts, then the measured dc output will be 25mv above the comparator trip point. if the ripple increases to 80mv with vin = 25 volts, then the measured dc output will be 40mv above the comparator trip. the best way to mini- mize this e ect is to minimize the output ripple. to compensate for valley regulation it is often desirable to use passive droop. take the feedback directly from the output side of the inductor, placing a small amount of trace resistance between the inductor and output ca- pacitor. this trace resistance should be optimized so that at full load the output droops to near the lower regula- tion limit. passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. the use of 1% feedback resistors contributes typically 1% error. if tighter dc accuracy is required use 0.1% resistors. note that for the internal preset voltages, the fb accuracy of 1.25% for 0 to 85c already includes the tolerance of the internal resistors. the output inductor value may change with current. this will change the output ripple and thus the dc output voltage. the output esr also a ects the ripple and thus the dc output voltage. switching frequency variation the switching frequency will vary somewhat due to line and load conditions. the line variations are a result of a xed o set in the on-time one-shot, as well as unavoid- able delays in the external mosfet switching. as input voltage increases, these factors make the actual dh on- time slightly longer than the idealized on-time. the net e ect is that frequency tends to fall slightly with increas- ing input voltage. the frequency variation with load is due to losses in the power train from ir drop and switching losses. for a con- ventional pwm constant-frequency topology, as load increases the duty cycle also increases slightly to com- pensate for ir and switching losses in the mosfets and inductor. a constant on-time topology must also over- come the same losses by increasing the e ective duty cycle (more time is spent drawing energy from vin as losses increase). since the on-time is constant for a given vout/vin combination, the way to increase duty cycle is to gradually shorten the o -time. the net e ect is that switching frequency increases slightly with increasing load. layout guidelines as with any switch-mode converter, and especially a dual-channel converter, a good pcb layout is essential for optimum performance. the following guidelines should be used for pcb layout. placement note that the pins on the ic are arranged in four groups, i.e. side1 power, side2 power, side1 analog, and side2 analog, as shown in figure 21. lx1 bst1 vdd1 dl1 en1 ss1 lx2 bst2 vdd2 dl2 en2 ss2 dh1 ilim1 pgd1 pgd2 ilim2 dh2 vout1 fb1 rtn ton fb2 vout2 gnd (pad) 1 7 6 12 13 18 19 24 SC416 side 1 power/gate drive side 2 power/gate drive side 1 analog side 2 analog figure 21 applications information (continued)
SC416 26 for placement, power devices for side1 should be grouped together near the gate drive pins for side1 (pins 23-24 and 1-8). power devices for side2 should be grouped together near the gate-drive pins for side2 (pins 15-20). the feedback and vout sense components should be located near the fbx/voutx pins. this includes the feed- back resistors and capacitors if used. ground connections when doing placement, be aware that there are four grounds to consider on the pcb. power ground for side1 power ground for side2 analog ground for side1 analog ground for side2 note that grounds (1) and (2) are high-current and con- tain high noise. these grounds carry the dl gate drive current as well as the high switching current through the mosfets and low-side diode. it is important to note that the SC416 has only one power ground pin (pad, pin 25), which must drive dl for both side1 and side2. as such, the low-side mosfet and diode will need to be near the ic. grounds (3) and (4) are low-current and intended for low-noise vout/fb ripple sensing. note that there is only one analog ground pin (rtn, pin 9) which shared between sides 1 and 2 proper connection between the grounds is needed for good operation. generally, all ground connections be- tween the power components and the SC416 should be short and direct, without vias where possible. each side has signi cant high-current switching in the ground path, moving between the input capacitors, the low-side mosfet, the low-side diode if used, and the output ca- pacitors. moreover, each side has signi cant high-cur- rent pulses to/from the ground pad, created by the dl 1. 2. 3. 4. drive to the low-side mosfets. the dl gate-drive cur- rent peaks can be 2 amps or more, with fast switching. as such the ground connection between the low-side mos- fets and the ground pad should be as short and wide as practical. note that the ground pad, which is the return path for the high-noise dl drive current, is not accessible on the top layer of the pcb, due to the other pins. the ground pad connection to the mosfets must therefore be done on an inner or bottom layer. for this reason, it is best to place the low-side mosfet on the opposite side of the pcb, to allow a wide and direct connection to the ground pad on the bottom layer. otherwise an inner layer must be used for the ground pad connection; if needed, this should be done with many vias to minimize the high-fre- quency impedance. this applies to both side1 and side2 mosfets. the remaining power devices should then be placed with their ground pins near each other, and near the ic. that is, the ground connections between the ic, the low- side mosfet, the low-side diode (if used), the input ca- pacitors, and the output capacitor, should be short. the other non-ground power connections (from input cap to high-side mosfet, from mosfets to inductor, and from inductor to output capacitor) should be short and wide as well, to minimize the loop length and area. use short, wide traces from the dl/dh pins to the mos- fets to reduce parasitic impedance; the low-side mos- fet is most critical. maintain a length to width ratio of <20:1 for gate drive signals. use multiple vias as required for current handling (and to reduce parasitics) if routed on more than one layer. when placing the power components, also be aware that the vout signal must route back to the analog compo- nents. it is important that this feedback signal not cross the dh/dl/bst or other high-noise power signals. place and rotate the power components in a way that allows the vout trace to get from the output capacitor to the applications information (continued)
SC416 27 analog components without crossing the high-noise power signals (dh/dl/bst, etc). the analog components are those which connect to the fb and vout pins. the fb pins are sensitive so the cop- per area of these traces should be minimized. compo- nents connected to fb should be placed directly near the ic and should not be placed over or near the gate drive or power signals (dl/dh/bst/ilim/lx/vdd). the connection between power ground (pad) and ana- log ground (rtn) should be done at a single point direct- ly at the ic. the analog components should be placed in their own ground island which connects to the pad directly at the ic, and all analog components should con- nect directly to this island. overall placement should look similar to figure 22. figure 22 applications information (continued) gnd (pad) SC416 side 1 power components side 2 power components side 1 analog components side 2 analog components the vdd supply decoupling capacitors should connect to the ic with short traces, with multiple vias if needed. connect the ilim traces to the low-side mosfet directly at the drain pins, and route these traces over to the ilim resistor on another layer if needed. route the vout/fb feedback traces in a quiet layer, away from noise sources. avoid routing near any of the high-noise switching signals or other noise sources.
SC416 28 typical characteristics 1.76 1.77 1.78 1.79 1.8 1.81 1.82 1.83 1.84 10 11 12 13 14 15 16 17 18 19 20 0a 1a 4a 10 a 1.47 1.48 1.49 1.5 1.51 1.52 1.53 10 11 12 13 14 15 16 17 18 19 20 10a 4a 1a 0a 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 012345678910 20v 15v 10v 1.47 1.48 1.49 1.50 1.51 1.52 1.53 012345678910 10v 15v 20v vout2 line regulation 1.5v psave enabled vout1 line regulation 1.8v psave enabled vout2 load regulation 1.5v psave enabled vout1 load regulation 1.8v psave enabled vout (v) vout (v) vin (v) vin(v) load (a) load (a) vout (v) vout (v) freq (khz) frequency vs. load, vout1 at 1.8v 260 270 280 290 300 310 320 330 340 350 345678910 10v 15v 20v frequency vs. load, vout2 at 1.5v 340 350 360 370 380 390 400 410 420 430 345678910 10v 15v 20v freq (khz) load (a) load (a)
SC416 29 typical characteristics vout1 e ciency, 1.8v psave enabled vout2 e ciency, 1.5v psave enabled vout1 e ciency, 1.8v psave disabled vout2 e ciency, 1.5v psave disabled eff (%) 60% 65% 70% 75% 80% 85% 90% 95% 100% 012345678910 10v 20v 15v 60% 65% 70% 75% 80% 85% 90% 95% 100% 012345678910 10v 20 v 15v load (a) load (a) eff (%) 60% 65% 70% 75% 80% 85% 90% 95% 100% 012345678910 10v 20v 15v 60% 65% 70% 75% 80% 85% 90% 95% 100% 012345678910 10v 20 v 15v eff (%) eff (%) load (a) load (a) load step vout1, 1.8v load step vout2, 1.5v
SC416 30 typical characteristics load release vout1, 1.8v psave disabled load release vout2, 1.5v psave disabled load release vout1, 1.8v psave enabled load release vout2, 1.5v psave enabled independent startup vout1, 1.8v no load independent startup vout2, 1.5v no load
SC416 31 typical characteristics proportional tracking startup proportional tracking shutdown independent shutdown vout1, 1.8v no load independent shutdown vout1, 1.8v no load coincident tracking startup coincident tracking shutdown
SC416 32 applications information (continued) component value manufacturer part number web c1,c2,c5,c6 10uf, 25v murata grm32dr71e106ka12l www.murata.com c10,c11 330uf/6m/2v panasonic eefsx0d331xr www.panasonic.com d1,d2 200ma/30v onsemi bat54a www.onsemi.com d3,d4 1a/40v onsemi mbsr140lt3 www.onsemi.com l1,l2 1.5uh/19a vishay ihlp5050cer1r5m01 www.vishay.com q1,q2 30v/12.5m i.r. irf7821 www.irf.com q3,q4 30v/12.5m i.r. irf7832 www.irf.com reference design en2 c15 100nf 4 1 2 3 5 6 7 8 9 d q4 irf7832 vout2 +5v c19 100nf r5 14k c21 no_pop r7 10k 4 1 2 3 5 6 7 8 9 d q2 irf7821 c14 1uf pgd2 c16 1uf 4 1 2 3 5 6 7 8 9 d q3 irf7832 c22 100nf r3 6.81k r4 6.81k c12 100nf vin c2 10uf c1 10uf c3 0.22uf c18 10nf c23 330pf r2 100k r1 100k c17 10nf +5v vout1 + c10 330uf +5v c20 no_pop vin power input c9 100nf r6 10k lx1 1 bst1 2 vdd1 3 dl1 4 en1 5 ss1 6 vout1 7 fb1 8 rtn 9 ton 10 fb2 11 vout2 12 ss2 13 en2 14 dl2 15 vdd2 16 25 pad dh2 19 ilim2 20 lx2 18 bst2 17 pgd1 22 pgd2 21 ilim1 23 dh1 24 u1 SC416 bat54a d2 1.8v at 10a r8 1meg + c11 330uf +5v +5v bat54a d1 1.5v at 10a vin vin c6 10uf vin power input c5 10uf c4 0.22uf r9 10k vout2 c7 100nf en1 c8 100nf l2 1.5uh d3 140l d4 140l 4 1 2 3 5 6 7 8 9 d q1 irf7821 c13 100nf vout1 l1 1.5uh pgd1 bill of materials
SC416 33 outline drawing - mlpq-24 e1 e bxn d/2 1 2 n e1 .100 .106 .110 2.55 2.70 2.80 pin 1 indicator 4.15 3.85 4.00 4.15 3.85 .157 .151 .163 .151 .163 aaa c a c (laser mark) d e b a1 a a2 seating plane lxn e/2 bbb c a b d1 inches .020 bsc b .007 bbb aaa n d1 e l e d .011 .100 dim a1 a2 a min .000 - .031 0.30 0.18 .012 0.25 .010 0.50 2.80 0.30 2.55 .004 .004 24 .016 .157 .106 .020 .110 0.10 0.10 24 0.40 4.00 2.70 0.50 bsc millimeters max 0.05 - 1.00 dimensions min 0.00 - nom (.008) .035 .001 max .002 - .040 nom 0.80 0.02 (0.20) 0.90 controlling dimensions are in millimeters (angles in degrees). coplanarity applies to the exposed pad as well as the terminals. notes: 2. 1.
semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com contact information SC416 34 land pattern - mlpq-24 this land pattern is for reference purposes only. consult your manufacturing group to ensure your notes: 1. dim x y h k p c g millimeters inches (3.95) .010 .033 .122 .021 .106 .106 (.155) 0.25 0.85 2.70 0.50 2.70 3.10 dimensions company's manufa cturing guidelines are met. 4.80 .189 z k g z h (c) x p

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